1. Field of the Invention
The present invention relates to a memory control unit for a DDR-SDRAM.
2. Description of the Related Art
DDR memories such as DDR1-SDRAMs and DDR2-SDRAMs are becoming a mainstream of DRAM (Dynamic Random Access Memory) used as high capacity memories. Especially, it is standardized that the DDR2-SDRAMs have clock rate of 400 MHz-800 MHz according to the specification of the JEDEC (Joint Electron Device Engineering Council).
As the operating speed of the DDR-SDRAMs is increased, the influence of wiring delay and skew between a memory control LSI and a memory LSI on a substrate is increasing. It is therefore becoming difficult to develop an ASIC (Application Specific Integrated Circuit) and connect it to a high-speed DDR-SDRAM.
For example, in the case of a DDR266, which is an interface for DDR-SDRAM and has a clock frequency of 133 MHz, it is possible to develop a memory control ASIC based on estimated wiring delay and skew on a substrate with a small number of memories mounted thereon and on a substrate with a large number of memories mounted thereon. On the other hand, DDR2-533 has a clock frequency as great as 266 MHz, and DDR2-800 has a clock frequency as great as 400 MHz. Accordingly, the influence of the wiring delay and skew is relatively greater. If the wiring delay and skew are wrongly estimated and ASICs are developed based on the wrong estimate, there is a high likelihood that the ASICs cannot be used. Moreover, because the wiring delay and skew amount differ depending on the type, the number, and the layout of memories to be connected, it will possibly be necessary to develop an ASIC for each substrate.
FIG. 8A is a timing chart of SDRAM waveforms in the vicinity of a terminal of a memory control ASIC. FIG. 8B is a timing chart of SDRAM waveforms in the vicinity of a terminal of a memory. FIGS. 8A and 8B each show waveforms of CK (memory clock), Address/Ras/Cas/We (address and command), Cs (chip select), DQS [3:0] (data strobe), DQ [31:0] (data bus), and DM [3:0]. As is clear from a comparison between FIG. 8A and FIG. 8B, since the amounts of wiring delay and skew are constant regardless of the clock cycle, the shorter the clock cycle, the greater the influence of the wiring delay and skew.
FIG. 7 shows an example of a standard for the write side of DDR2-SDRAM. As is obvious from the figure, the shorter the clock cycle, the more attention needs to be paid to the skew on the substrate when developing an ASIC.
Japanese Patent Laid-Open Publication No. 2005-56334 discloses, as a DDR interface that loads data signals on the rising and falling edges of a data strobe signal, a data loading circuit capable of eliminating the difference in delay between the data signals. Japanese Patent Laid-Open Publication No. 2004-126772 discloses a memory controller for inputting digital data to and outputting digital data from a semiconductor storage device such as a DDR-SDRAM. This memory controller is capable of accurately synchronizing a strobe signal generated from a clock signal with the digital data. Japanese Patent Laid-Open Publication No. 2005-78547 discloses a semiconductor integrated circuit that precisely and stably synchronizes signals loaded from an external DDR-SDRAM.